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NXP Semiconductors /LPC408x_7x /PWM0 /IR

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Interpret as IR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PWMMR0INT)PWMMR0INT 0 (PWMMR1INT)PWMMR1INT 0 (PWMMR2INT)PWMMR2INT 0 (PWMMR3INT)PWMMR3INT 0 (PWMCAP0INT)PWMCAP0INT 0 (PWMCAP1INT)PWMCAP1INT 0RESERVED 0 (PWMMR4INT)PWMMR4INT 0 (PWMMR5INT)PWMMR5INT 0 (PWMMR6INT)PWMMR6INT 0RESERVED

Description

Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending.

Fields

PWMMR0INT

Interrupt flag for PWM match channel 0.
PWMMR1INT

Interrupt flag for PWM match channel 1.
PWMMR2INT

Interrupt flag for PWM match channel 2.
PWMMR3INT

Interrupt flag for PWM match channel 3.
PWMCAP0INT

Interrupt flag for capture input 0
PWMCAP1INT

Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR).
RESERVED

Reserved. Read value is undefined, only zero should be written.
PWMMR4INT

Interrupt flag for PWM match channel 4.
PWMMR5INT

Interrupt flag for PWM match channel 5.
PWMMR6INT

Interrupt flag for PWM match channel 6.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data